Views: 0 Author: Site Editor Publish Time: 2025-03-05 Origin: Site
The global server market size in 2023 is about 130 billion US dollars, with a compound annual growth rate of 8%. Cloud computing, AI computing power demand, and edge computing are the main driving factors. Cloud computing data centers continue to expand, enterprises' demand for AI computing power has exploded, and edge computing application scenarios have expanded, driving the expansion of the server market.
The global switch market size will be $35 billion in 2023, with a compound annual growth rate of 7%. Data center expansion and 5G network deployment are the main driving forces. The scale of data centers continues to expand, network architecture is upgraded, and 5G network construction is accelerated. The demand for switches continues to rise, driving the growth of the market size.
The widespread use of high-speed interfaces such as PCIe 5.0/6.0 and 400G Ethernet has led to a surge in demand for TVS/ESD devices, bringing huge opportunities to the related device market.As the performance of servers and switches improves, the number of high-speed interfaces increases, and the performance requirements for protection devices increase, the TVS/ESD device market is entering a period of rapid development.
The server adopts advanced technologies such as high-density power design (48V DC power supply), liquid cooling, and chiplet heterogeneous computing, but faces technical pain points such as high-speed signal integrity (25G+ SerDes) and power noise suppression. High-density power design requires devices to have high reliability and low power consumption, and liquid cooling places higher requirements on device heat dissipation performance. Chiplet heterogeneous computing needs to solve the signal integrity problem in multi-chip collaborative work.
Switch technology routes include low-power ASIC chips, PoE++ (90W power supply), optical module integration, etc. The technical pain points are mainly concentrated in high-speed signal integrity and power supply noise suppression. Low-power ASIC chips require optimized circuit design to reduce power consumption. PoE++ power supply requires devices to have high efficiency and high reliability. Optical module integration places higher requirements on signal integrity and electromagnetic compatibility.
For high-speed signal integrity issues, low-capacitance TVS devices (such as less than 3pF) are needed; for power supply noise suppression, high-frequency low-loss inductor devices (such as ferrite cores) are needed to meet the technical requirements of servers and switches. Low-capacitance TVS devices can effectively protect high-speed signals from interference, and high-frequency low-loss inductor devices can suppress power supply noise, ensure stable operation of equipment, and improve overall performance.
Standard Type | Standard No. | Standard Name/Scope | Scope of application | Test content |
Network Communication | IEEE 802.3 | Ethernet standards (such as 802.3ae 10G Ethernet) | Switch physical layer and data link layer interface | Transmission rate, frame format, bit error rate, compatibility test |
RFC 2544 | Network Equipment Performance Test Standards | Switch throughput, latency, and packet loss rate | Traffic load test, back-to-back frame test | |
Server | ISO/IEC 11801 | Information technology - Universal cabling standard for user buildings | Server room wiring, connectors | Transmission performance and anti-interference test |
TIA-568-D | Commercial Building Communications Cabling Standards | Data Center Cabling System | Channel bandwidth, return loss test | |
Storage | SNIA SMI-S | Storage Management Interface Specification | Unified storage device management interface | API compatibility and multi-vendor device interoperability testing |
General Security | ISO/IEC 27001 | Information Security Management System | IT equipment full life cycle security management | Access control, data encryption, and vulnerability management process audits |
Standard type | Standard No. | Standard name/scope | Scope of application | Test content |
Network Communication | YD/T 1099-2023 | Ethernet switch technical requirements | Enterprise-class switches sold in China | VLAN, STP protocol consistency test, security function (ACL, anti-attack) |
GB/T 36627-2018 | Information security technology - Network switch security technical requirements | Switch security baseline (such as log audit, port isolation） | Security vulnerability scanning, permission management testing | |
Server | GB/T 26245-2021 | Minimum energy efficiency values and energy efficiency grades for microcomputers | Server Energy Consumption and Efficiency | No-load/full-load power consumption test, power conversion efficiency |
GB/T 32910-2016 | Information technology - General specifications for servers | Basic server performance (CPU, memory, storage scalability) | Stability stress test (such as 72 hours of continuous load) | |
Storage | YD/T 2435-2018 | Storage Area Network (SAN) Technology Requirements | Storage device interconnection protocols (such as iSCSI, FC) | Data transmission bandwidth and redundant switching test |
Standard type | Standard No. | Standard name/scope | Scope of application | Test content |
Huawei | Q/HW Standard Series | Huawei Enterprise Network Equipment Technical Specifications (such as CloudEngine switches) | Huawei's self-developed switches/servers (such as high-density ports, SDN support) | Verification of custom traffic scheduling algorithm, compatibility test between CloudEngine and usionSphere cloud platform |
HPE | HPE ProLiant Series Specifications | HPE server design standards (such as Gen11 server cooling design) | HPE server hardware reliability | High temperature and high humidity environment operation test, fault switching time (<30 seconds) |
wave | Inspur InCloud OpenStack Specifications | Inspur Cloud Server and Open Source Platform Integration Standard | Inspur servers are compatible with open source cloud platforms (such as OpenStack/K8S) | Virtualization resource scheduling efficiency test, API call delay |
High-density PCB layout leads to increased crosstalk risk, making it difficult to ensure signal integrity, and placing higher demands on EMC design. In a limited PCB space, the distance between high-speed signal lines is reduced, which can easily generate electromagnetic interference and affect signal transmission quality.
Multi-port high-speed communications (such as PCIe and DDR5) have strict requirements on signal integrity. Any slight interference may cause communication errors. The rising and falling edge times of high-speed signals are extremely short, and the signal integrity requirements are extremely high. Strict control of signal transmission paths and electromagnetic interference is required.
