
Placing equalizing resistors close to voltage sampling channels can generate significant electromagnetic interference. Large currents flowing through the equalizing resistors produce thermal noise and alternating magnetic fields, easily inducing noise voltages in sensitive sampling loops and interfering with sampling accuracy. The solution is to centrally position the equalizing resistor array away from the analog sampling circuitry. Design a separate loop with minimal area for the equalizing current path. Sampling lines should use differential routing and be routed on inner layers of the PCB as much as possible, utilizing the ground plane and power areas for isolation. If necessary, add slots between the equalizing resistor area and the sampling area to enhance isolation. Physical partitioning and optimized routing can effectively ensure interference-free sampling.