How to suppress resonance in the layout of EPS bus capacitors?

The layout of the DC-Link capacitors in an EPS directly affects its ability to suppress resonance and high-frequency noise. Improper layout can introduce parasitic inductance, forming a resonant circuit with the capacitor itself. Suppression methods:

1. Close to power devices: Place the DC-Link capacitors as close as possible to the DC input pins of the inverter bridge or switching transistors, preferably directly on the module terminals, to minimize the parasitic inductance of the busbar.

2. Use a low-inductance structure: Use multilayer busbars or make the positive and negative copper foils parallel and close together, using the mutual inductance between the positive and negative layers to cancel out some of the inductance.

3. Parallel connection of multiple capacitors: Use multiple small-capacity film capacitors in parallel instead of a single large capacitor. Parallel connection can reduce the equivalent series inductance (ESL) and distribute the layout to cover a wider frequency band.

4. High-frequency decoupling: Connect additional low-ESL ceramic capacitors (such as X7R, NPO material) in parallel at the switching transistor pins to provide the shortest path for the highest frequency current ripple.

The layout goal is to achieve the shortest, low-inductance high-frequency current loop.