How to suppress power supply ripple in a concentrator?

Ripple generated by the internal switching power supply of the concentrator can interfere with precision acquisition and communication circuits. Suppression requires multi-stage processing at the source, transmission, and load ends. At the source, the switching power supply feedback loop is optimized, the output capacitor value is increased, and low-ESR polymer capacitors are selected. RC snubbers (e.g., 1nF + 2.2Ω) are added at the switching node to mitigate voltage spikes.

On the transmission path, a two-stage LC filter is added at the DC/DC output, using a PBZ1608E600Z0T ferrite bead (60Ω@100MHz) and a low-ESR ceramic capacitor (22μF, X5R). For the load end (e.g., ADC, reference source), a linear regulator (LDO) is used for post-stage regulation, with π-type filters placed before and after it. The PCB layout ensures that the power loop area of the switching power supply is minimized and located away from the analog area. Through comprehensive suppression, the switching ripple on the 5V power bus can be reduced from 80mVpp to below 5mVpp, and high-frequency noise (>1MHz) is attenuated by 30dB, ensuring the performance of the 16-bit ADC.