How to design a power conduction immunity protection circuit for edge boxes?

The edge box's 24V DC power supply conduction immunity requires withstanding 10Vrms 0.15-80MHz interference signal protection circuitry. The circuitry employs a three-stage structure:

Stage 1: Parallel varistor 14D391K (14D diameter, 391 varistor voltage 390V K, standard type, absorbs high-energy low-frequency interference);

Stage 2: Series common-mode inductor CML4532A-101T (CML series 4532, 4.5×3.2mm, 101T, 100μH inductance, presents high impedance to common-mode interference);

Stage 3: Parallel TVS 5.0SMDJ33CA (5.0SMDJ 5000W, SMC package, 33V, Rule B, nominal breakdown voltage 33V, actual VRWM=28.2V, clamped at 53.3V, clamping residual voltage to a safe value).

Simultaneously, a 470pF 2kV power supply is connected in parallel to the PE. The Y capacitor provides a return path for the common-mode current. A 100μF electrolytic capacitor is connected in parallel after the inductor to smooth residual ripple. The PCB layout should follow the flow direction of varistor-common-mode inductor-TVS. The TVS must be close to the DC-DC input terminal. In the IEC61000-4-6 10V test, the power supply fluctuation is less than ±1% and there is no reset or restart phenomenon.