
In fast charging mode, the rapid switching of high current at the charging interface can lead to significant conducted interference, easily resulting in peak values exceeding limits at the switching frequency and its harmonics. This is because the current change rate di/dt is extremely high, generating common-mode and differential-mode noise through the parasitic parameters of the charging cable. Suppression measures include installing high-performance common-mode inductors and high-current differential-mode inductors close to the positive and negative terminals of the power line at the charging interface to form a π-type filter network. Simultaneously, low-ESR electrolytic capacitors and MLCC capacitors are used in parallel for energy storage and decoupling. The PCB layout must ensure that the filtering components are close to the interface, and that the high-current path is as short and wide as possible to reduce loop area and parasitic inductance.