How to suppress power supply ripple in an FTU?

Power supply ripple affects FTU sampling accuracy and control stability. The suppression scheme employs a combination of multi-stage filtering and voltage regulation. The input uses a π-type filter: a CMZ3225A-501T common-mode inductor (500μH) + a 470μF/100V electrolytic capacitor + a 100nF/100V ceramic capacitor. The DC-DC output uses a PWRA6045R6R8M0T power inductor (6.8μH) + a 220μF/25V POSCAP capacitor + a 10μF/25V ceramic capacitor. The LDO is a TPS7A4701 with a noise level of 4μVRMS. PCB layout: filter capacitors are placed as close to the IC as possible, the power layer is intact, and the loop area is reduced. With this scheme, power supply ripple can be suppressed to below 10mVpp, and the noise spectrum is reduced by 40dB in the 100kHz-1MHz range, meeting the IEC 61000-4-17 voltage fluctuation test requirements.