How to minimize the loop area of the sampling loop of a power FTU?

Minimizing the sampling loop area reduces magnetic field coupling. Twisted-pair differential transmission and PCB optimization are employed. Current sampling: Twisted-pair shielded cable with a 20mm twist pitch is used, resulting in a loop area of less than 1cm². Voltage sampling: Coaxial cable or twisted-pair cable is used. PCB design: Differential pair traces are used for sampling inputs, with a trace width of 0.2mm, a spacing of 0.2mm, and minimized parallel length. The ADC circuit is placed close to the sampling interface, with differential trace lengths less than 50mm. A complete ground plane is provided below the sampling loop, prohibiting other signal lines from crossing it. This design reduces the sampling loop area to 10% of traditional designs, lowers magnetic field-induced noise by 30dB, and improves sampling accuracy to 0.1 class, meeting the requirements of IEC 61869 standard.