How to control the minimum loop of the inverter power board

Minimizing the loop area of the inverter power board is the most effective measure to reduce magnetic field radiation and conducted interference. The power loop mainly refers to the circuit formed by the DC bus capacitor, IGBT module, and connecting conductors. The rapidly changing di/dt in this loop generates a strong magnetic field. Control methods include: using stacked busbar technology to tightly stack the positive and negative DC buses, separating them with a thin insulating layer, so that the magnetic fields generated by the positive and negative currents cancel each other out, greatly reducing the loop area and parasitic inductance. Optimizing component layout by mounting the DC bus capacitor as close as possible to the IGBT module.

Using multiple small capacitors in parallel instead of a single large capacitor, and symmetrically arranging them around the IGBT module to shorten the current path. In PCB design, for small power loops on the driver board, such as the gate drive loop, the traces should be kept short and wide, and close to the driver chip. Avoid long parallel traces of power lines and signal lines. Evaluate the loop inductance of different layouts using 3D modeling or simulation software to select the optimal solution. In actual products, scanning the power board surface with a near-field probe often reveals areas with strong magnetic fields corresponding to large loops, requiring targeted optimization. Eternity's custom multilayer busbar service and low-inductance, low-capacitance solutions are powerful tools to help engineers achieve minimum loop design for power boards.