How to design a multi-stage filter on the PAC (Power Controller Assembly) board?

The onboard multi-stage filtering design of the intelligent controller PAC requires a step-by-step attenuation strategy for different noise frequency bands.

The first stage is power input filtering, using a CMZ7060A-701T common-mode inductor and X2 capacitors to suppress differential-mode and common-mode noise below 150kHz. The second stage is DC/DC converter output filtering, using a PWRA6045 power inductor (6.8μH) and low-ESR solid-state capacitors to form an LC filter to handle noise from 100kHz to 1MHz. The third stage is chip-level decoupling, deploying P... BZ1608A-102Z0T ferrite beads (1000Ω@100MHz) and 0.1μF ceramic capacitors in 0402 packages filter out high-frequency noise above 10MHz; each stage is connected via a π-type or T-type network to ensure impedance mismatch and improve filtering effect; the layout follows the principle of large to small, with filtering components placed close to noise sources or sensitive devices; actual measurements show that this multi-stage filtering design can reduce PAC board-level power supply noise to below 50mVpp in the 10Hz-100MHz range, meeting the IEC61000-4-17 voltage fluctuation immunity requirements;