
To protect the PAC (Power Flow Controller) from EFT (Electrical Fast Burst) interference, filtering and shielding are required. At the power port, a common-mode inductor (CMZ7060A-701T) and X/Y capacitors form a filter, with a TVS (5.0SMDJ36CA) connected in parallel to absorb transients. At the signal port, a ferrite bead (PBZ1608A-102Z0T) is connected in series with a TVS (SMBJ6.5CA) in parallel. All port filtering components are placed close to the interface. The PCB uses a multi-layer board with a complete ground plane. Shielded cables are used, with both ends of the shield grounded. The software employs a watchdog timer and error correction mechanisms.
During testing, IEC61000-4-4 Level 4 (4kV, 5kHz repetition frequency) pulses are applied to both the power and signal lines, and the system function is not lost. Through design, the PAC can withstand EFT interference with a bit error rate of less than 10^-6.