How are high-speed and low-speed signals separated in a smart controller (PAC)?

Separating high-speed signals (such as clock and DDR bus) from low-speed signals (such as GPIO and I2C) in a PAC (Power Controller Architecture) can reduce crosstalk and radiation. During layout, high-speed signal layers (usually inner layers) and low-speed signal layers are arranged in layers, isolated by a ground plane. Within the same layer, high-speed signal traces and low-speed signal traces are isolated by grounded copper foil with a spacing greater than three times the trace width. High-speed signal lines use differential pairs (such as USB and Ethernet) and are strictly equal in length and tightly coupled. Low-speed signals can be routed at one end. For parallel buses, daisy-chain or fly-by topologies are used, with matching resistors (such as 22Ω) at the end. Simultaneously, common-mode inductors (such as CMZ2012A-900T) are used for isolation when high-speed signal lines cross regions. Simulation and actual measurements show that this separation design can reduce crosstalk from high-speed signals to low-speed signals to below -40dB, improve signal integrity eye diagram margin by 20%, and pass the IEC61000-4-3 radiated emission test.