How to improve EMC of multi-layer PAC and backplane PCB for intelligent controllers?

Improving the EMC performance of multilayer PAC and backplane PCBs for intelligent controllers requires attention to layer stack-up, layout, and interconnection. A symmetrical layer stack-up structure, such as a 10-layer board (S1/G2/S3/G4/P5/G6/S7/G8/S9/G10), ensures each signal layer is adjacent to a complete ground plane. Power layers should be rationally partitioned, with different power domains connected using ferrite beads (such as PBZ1608A-102Z0T). During layout, high-speed components should be placed close to connectors to shorten traces. The clock circuit should be placed in the center of the board.

Shielding is added; the backplane PCB uses orthogonal routing, and the signal lines of adjacent layers are perpendicular; high-speed connectors (such as HSD, FMC) are used for interconnection interfaces, and common-mode inductors (such as CMZ2012A-900T) and ESD protection (such as ESDLC5V0D3B) are placed at the interfaces; simulation and testing are combined, and after optimization, the radiated emission of the multilayer board is reduced by 15dB, and the backplane crosstalk is less than -50dB, which meets the IEC61000-4-3 and IEC61000-4-6 test standards;