
Ensuring the PAC (Power Actuator) does not crash during voltage dips and interruptions requires attention to both hardware and software.
On the hardware side, the power supply design utilizes a wide input range (e.g., 85-264VAC) switching power supply and increases the energy storage capacitor (e.g., 1000μF) to maintain short-term power supply. Critical circuits (such as the CPU and memory) use LDO (Low Voltage Regulator) staged voltage and include a power-down detection circuit to trigger a reset.
On the software side, a watchdog timer is enabled, and the system saves its state to non-volatile memory upon detecting a voltage dip.
Testing is conducted according to IEC61000-4-11/29, applying a voltage dip to 70% of the rated value for 10 cycles, followed by a 5ms interrupt; the system should not restart or should recover its state after restarting. Through this design, the PAC can withstand voltage anomalies, increasing its MTBF to 100,000 hours.