How to control the minimum loop of a power line carrier PLC?

To minimize the loop in the PLC power line carrier circuit, PCB layout and routing design need to be optimized. Differential pair routing is used for carrier signal lines, with a line width of 0.2mm and a spacing of 0.3mm, maintaining impedance matching (e.g., 100Ω). Loop area is reduced through tightly coupled routing, with parallel differential pair traces and a length matching error of less than 5mm. Power decoupling capacitors are placed close to the IC power pins to form localized small loops. A multilayer board is used, with the carrier signal layer adjacent to the ground plane layer to provide a mirrored return path. Critical loops are partially covered with shielding. The loop inductance is calculated through simulation, with a target value of less than 10nH. In actual testing, a near-field probe is used to scan the radiation; after optimization, the radiation intensity in the 30MHz-200MHz frequency band should be below 40dBμV/m. Controlling the loop area can reduce radiated emissions by 20dB, improving signal integrity.