How to improve EMC performance of a multilayer PLC board with power line carrier communication?

Improving the EMC performance of multilayer PLC boards using power line carrier technology requires optimizing the stack-up design and layout. A minimum of four layers should be used: a top signal layer, a power layer, a ground layer, and a bottom signal layer. The power and ground layers are adjacent, forming a parallel plate capacitor for effective decoupling. The signal layers are close to the ground layer to provide mirrored return current. Layer thickness distribution: signal layers are thin (0.1mm), while power and ground layers are thick (0.2mm) to reduce impedance. In terms of layout, digital, analog, and power layers are separated and isolated by ground planes. Critical signal lines are placed on inner layers to reduce radiation. Vias are used to connect the ground plane, reducing ground impedance. Board-level EMC performance is analyzed through simulation to optimize the design. In actual testing, both conducted and radiated emissions meet the EN55032 Class B limits with a margin greater than 6dB. Multilayer board design can improve EMC performance by 20dB and make the system more stable.