How to reduce EMI leakage in power line carrier PLC PCB vias?

Reducing EMI leakage from power line carrier PLC PCB vias requires optimizing via design and layout. The ratio of via diameter to pad diameter should be controlled within 1:2, for example, a 0.3mm via diameter and a 0.6mm pad diameter. Place grounding vias next to high-speed signal vias to form a shielding array with a spacing less than λ/10 (λ being the highest frequency wavelength). Use back-drilling to remove via stubs to reduce resonance. For power vias, use multiple vias in parallel to reduce impedance. Ensure smooth transitions at via-signal line connections to avoid impedance abrupt changes. Analyze via radiation through simulation and optimize the design to ensure radiation intensity is below 40dBμV/m. In actual testing, using a near-field probe to scan the via area should result in a leakage electric field below 30dBμV/m. Optimized via design can reduce EMI leakage by 15dB, improving system EMC performance.