How to optimize EMC for EPSSiC/MOSFET drivers?

For driving SiC or high-speed MOSFETs in EPS, due to their extremely high switching speed, EMC optimization requires exceptional precision:

1. Extremely low inductance layout: The drive loop (including the driver chip, gate resistor, and gate-source of the switching transistor) must be minimized. It is recommended to place the driver chip close to the power transistor, or even use an integrated driver module.

2. Fine-tuning of gate resistors: The gate resistor value needs to be finely optimized through double-pulse testing to achieve a balance between switching losses, voltage overshoot, and EMI. Asymmetrical driving (small turn-on resistance, slightly larger turn-off resistance) is often used to balance efficiency and EMC.

3. Use of active Miller clamping: Integrate or externally incorporate active Miller clamping functionality in the driver IC to prevent parasitic conduction and reduce the resulting additional switching noise.

4. Enhanced drive power supply decoupling: Use ultra-low ESL ceramic capacitors (such as multiple 0402 packages in parallel) to provide the driver IC with extremely clean and fast transient current.

5. Absolutely clean reference ground: The drive ground must be independent and connected only to the source pin of the driven transistor to prevent power ground noise intrusion.