How to suppress power ripple in intelligent low-voltage monitoring units?

Power supply ripple suppression employs multi-stage filtering and voltage regulation. The input uses a π-type filter: a CMZ3225A-501T common-mode inductor (500μH) + a 220μF/50V electrolytic capacitor + a 10μF/50V ceramic capacitor. The DC-DC output uses a PWRA6045R6R8M0T power inductor (6.8μH) + a 100μF/16V POSCAP capacitor + a 10μF/16V ceramic capacitor. The LDO is a TPS7A4701 with a noise level of 4μVRMS. PCB layout: filter capacitors are placed as close to the ICs as possible, and the power layer is complete. With this solution, power supply ripple can be suppressed to below 20mVpp, and the noise spectrum is reduced by 35dB in the 100kHz-1MHz range, meeting the IEC 61000-4-17 voltage fluctuation test requirements.