How to minimize the loop area of the sampling circuit in an intelligent low-voltage monitoring unit?

The sampling loop area is minimized using twisted-pair differential transmission and PCB optimization.

Current sampling: Twisted-pair shielded cable with a 15mm twist pitch.

Voltage sampling: Coaxial cable.

PCB design: Differential pair traces are used for the sampling input, with a trace width of 0.15mm and a spacing of 0.15mm. The ADC circuit is placed close to the sampling interface, and the differential trace length is less than 30mm. A complete ground plane is provided below the sampling loop. This design reduces the sampling loop area, lowers magnetic field-induced noise by 25dB, and improves sampling accuracy to 0.5 class.