How to optimize interference suppression above 10MHz through the combination of common mode inductance and Y capacitor?

Common mode inductors suppress interference by presenting a high common mode impedance from low to mid-to-high frequencies (e.g., below 1MHz). However, at high frequencies (above 10MHz), impedance decreases due to parasitic capacitance (between windings and between windings and the magnetic core), weakening the suppression effect. Y capacitors (usually ceramic capacitors, such as MLCC) feature low equivalent series resistance (ESR) and equivalent series inductance (ESL), providing a low-impedance path at high frequencies to shunt common mode interference to ground.

Optimization method:

Capacitance selection: The capacitance of the Y capacitor needs to match the parasitic capacitance of the common mode inductor to avoid resonance (which can amplify interference). Generally, a small capacitance Y capacitor ranging from 100pF to 1nF is chosen to ensure low impedance in frequency bands above 10MHz.

Layout coordination: The Y capacitor should be placed close to the output terminal of the common mode inductor (near the load side) to shorten the lead length and reduce parasitic inductance, thereby enhancing high-frequency shunting effect.

Multi-level combination: A multi-level structure of "common mode inductor + small capacitance Y capacitor" can be adopted, with the front-end inductor suppressing low and mid-frequencies and the rear-end Y capacitor enhancing high frequencies, forming a low-pass filtering network covering a wide frequency band