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When using common mode inductance in conjunction with differential mode inductance, how should the parameters of the two be matched?

Time：2025-12-30 Views：41次

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Common mode inductance suppresses common mode interference (symmetric interference between two wires to ground), while differential mode inductance suppresses differential mode interference (asymmetric interference between two wires). Parameter matching requires complementary frequency coverage: the effective suppression frequency band of common mode inductance (such as 1kHz-100MHz) and the differential mode inductance (such as 50Hz-10MHz) should overlap smoothly to avoid suppression blind spots. Generally, the resonant frequency of differential mode inductance is slightly higher than that of common mode inductance, covering low-frequency differential mode interference (such as power supply ripple). Impedance matching: the common mode impedance of common mode inductance should be much larger than the common mode impedance of the circuit (such as ≥10 times), and the differential mode impedance of differential mode inductance should be much larger than the differential mode impedance of the circuit to ensure effective attenuation of interference. Current compatibility: the rated current of differential mode inductance should match the operating current of the circuit (to avoid saturation), and the rated current of common mode inductance should consider the superposition of common mode current and differential mode current, with both requiring a 20%-50% margin. Core saturation characteristics: differential mode inductance should use a core with high saturation flux density (such as Sendust) to avoid saturation caused by high differential mode current; common mode inductance should use a core with high magnetic permeability (such as ferrite) to prioritize common mode suppression capability

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When using multiple common mode inductors in series, how can we avoid the overlap of resonance points?

2025-12-30

The resonance of common-mode inductance is determined by its inductance (L) and parasitic capacitance (C, such as inter-winding capacitance), with the resonance frequency f0=1/(2πLC). When multiple stages are connected in series, if the resonance points are close, it can lead to a sharp decrease or even amplification of interference suppression in a certain frequency band. To avoid the overlap of resonance points, differentiated design methods are employed: by adjusting the parameters of each inductance (such as core material, number of turns, winding structure), the resonance points of each stage are staggered. For example, the front stage uses a high permeability core (such as manganese-zinc ferrite) to increase inductance and reduce resonance frequency; the rear stage uses a low permeability core (such as nickel-zinc ferrite) to decrease inductance and increase resonance frequency, ensuring that the resonance point spacing is ≥2 octaves. Introducing damping: connecting small resistors (such as 10-100Ω) between stages to consume resonance energy and suppress resonance peaks, without significantly affecting the common-mode impedance. Parasitic capacitance control: the rear stage inductance adopts layered winding or adds a shielding layer to reduce parasitic capacitance, shifting the resonance frequency to a higher frequency band and complementing the front stage

How to optimize interference suppression above 10MHz through the combination of common mode inductance and Y capacitor?

2025-12-30

Common mode inductors suppress interference by presenting a high common mode impedance from low to mid-to-high frequencies (e.g., below 1MHz). However, at high frequencies (above 10MHz), impedance decreases due to parasitic capacitance (between windings and between windings and the magnetic core), weakening the suppression effect. Y capacitors (usually ceramic capacitors, such as MLCC) feature low equivalent series resistance (ESR) and equivalent series inductance (ESL), providing a low-impedance path at high frequencies to shunt common mode interference to ground Optimization method: Capacitance selection: The capacitance of the Y capacitor needs to match the parasitic capacitance of the common mode inductor to avoid resonance (which can amplify interference). Generally, a small capacitance Y capacitor ranging from 100pF to 1nF is chosen to ensure low impedance in frequency bands above 10MHz. Layout coordination: The Y capacitor should be placed close to the output terminal of the common mode inductor (near the load side) to shorten the lead length and reduce parasitic inductance, thereby enhancing high-frequency shunting effect. Multi-level combination: A multi-level structure of "common mode inductor + small capacitance Y capacitor" can be adopted, with the front-end inductor suppressing low and mid-frequencies and the rear-end Y capacitor enhancing high frequencies, forming a low-pass filtering network covering a wide frequency band

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