How to suppress resonance in the bus capacitor layout of an energy storage system PCS?

The layout of the DC-Link capacitors in a PCS directly affects its ability to suppress resonance and high-frequency noise. Improper layout can introduce parasitic inductance, forming a resonant circuit with the capacitor itself. Suppression methods:

1. Close to power devices: Place the DC-Link capacitors as close as possible to the DC input pins (P, N) of the IGBT module, preferably directly on the module terminals, to minimize the parasitic inductance of the busbar.

2. Use a low-inductance structure: Use multilayer busbars or flat copper strips connected in parallel and close proximity, utilizing the mutual inductance between the positive and negative layers to cancel out some of the inductance.

3. Parallel connection of multiple capacitors: Use multiple small-capacity film capacitors in parallel instead of a single large capacitor. Parallel connection reduces the equivalent series inductance (ESL) and disperses the layout to cover a wider frequency band.

4. High-frequency decoupling: Connect additional small-capacity, low-ESL ceramic capacitors in parallel at the switching transistor pins to provide the shortest path for the highest frequency current ripple.