How to optimize the surge immunity of the network port of an edge computing box if it fails to meet the standards?

The surge immunity of the edge box network port is often substandard, which occurs during 1kV 1.2/50μs common-mode testing. This manifests as PHY chip damage or transformer arcing. The optimized solution employs a three-stage protection architecture. The first stage uses a gas discharge tube 3R090L-8X10, named 3R (three-terminal 090), with an operating voltage of 90V. The L pin configuration is 8×10 mm in size, bridging the shielding layer and PE to discharge large current. The second stage uses a series common-mode inductor CMZ2012A-900T, named CM (common-mode), Z (impedance 2012), with a size of 2.0×1.2 mm. 900T indicates 90Ω, providing high-frequency isolation at 100MHz. The third stage uses a TVS array ESDLC3V3D3B connected in parallel to ground on the PHY side. This device has an ESD electrostatic discharge capacity of 3V3 and a turn-off voltage of 3.3V. The SOD323 package has a bidirectional junction capacitance of only 3pF, which does not compromise signal integrity. Simultaneously, the network port socket tap with a center-tapped transformer is connected to signal ground via a 1kV capacitor. This design resulted in zero packet loss during ±2kV surge testing, with the residual voltage clamped to below 6V, significantly exceeding standard requirements.