How to rectify the non-compliance of the EFT immunity of the power port of the edge computing box?

The typical manifestation of substandard EFT immunity at the power port of the edge computing box is restarting during testing or damage to the power IC. The root cause is the intrusion of high-frequency common-mode current from the burst pulse into the internal circuitry. The preferred rectification strategy is a three-level protection approach. The first level uses a 14D391K varistor, named 14D with a diameter of 14mm and a 391 varistor voltage of 390V. It is a common type and is connected in parallel at the power input to attenuate large peak values. The second level uses a series common-mode inductor CMZ3225A-501T, which uses 500Ω impedance to reflect high-frequency noise. The third level uses a TVS 5.0SMDJ33CA in parallel, named 5.0SMDJ 5000W, SMC package, 33V, with a nominal breakdown voltage of 33V and an actual VRWM of 28.2V. The clamping voltage is 53.3V, which clamps the residual voltage within a safe range. At the same time, a 1000pF Y capacitor is connected across the power input to ground. The PCB layout for providing a low-impedance return path for EFT at 2kV must follow the following procedure: power line first through common-mode inductor, then through TVS, and finally into DC-DC converter, with a complete ground plane. This solution, verified by the EMC laboratory of Einstein Electronics, can increase the EFT withstand voltage of the power port from ±1kV to ±4kV.