How to suppress current sampling interference in power FTUs?

Current sampling interference originates from the secondary side of the current transformer (CT) and the transmission line. Suppression scheme: A 100Ω/2W load resistor and a 0.1μF/100V capacitor are connected in parallel on the CT secondary side. Shielded twisted-pair cable with a 20mm twist pitch is used for the sampling line. The PCB input stage uses a CMZ3225A-201T common-mode inductor (200μH) for filtering, coupled with ESDLC5V0D3B protection. The operational amplifier circuit uses an AD8629 with a second-order active filter and a cutoff frequency of 2kHz. PCB layout: The sampling loop area is minimized, and differential routing is used. Through this suppression, the current sampling accuracy reaches level 0.2, and the common-mode rejection ratio is greater than 100dB, meeting the requirements of IEC 61869 standard and IEC 61000-4-8 power frequency magnetic field immunity test.