Has the PCB layout of the industrial AI edge gateway been optimized for EMC in relation to the AI chip?

The industrial AI edge gateway PCB design implements EMC optimizations tailored to the characteristics of the AI chip:

1. The AI core power supply uses a large copper area and places high-frequency decoupling capacitors (0.1μF, 1μF, 10μF) close to the chip.

2. The DDR4 differential clock is strictly equal in length and spacing with an error of <5mil and is connected in series with a 22Ω resistor.

3. The PCIe Gen3 signal packet ground spacing is <2mm and the number of vias is ≤2.

4. A ground plane is laid under the AI chip and densely packed with vias for heat dissipation while reducing ground impedance.

5. The HDMI and MIPI interfaces are connected in series with a CMZ20212A-900T common-mode filter to suppress common-mode radiation.

After these optimizations, the radiated emission of the AI chip at full load is reduced by 15dB compared to the initial version.