How to suppress clock radiation in a smart controller (PAC)?

The clock circuit (such as crystal oscillator and PLL) of the intelligent controller PAC is the main source of frequency radiation. Suppression needs to be addressed from three aspects: source, path, and antenna. For the source, a low-jitter, low-rise-time crystal oscillator is selected, and spread spectrum (SSC) technology is used to broaden the spectrum. A low-pass filter is formed by connecting a PBZ1005B-501Z0T ferrite bead (500Ω@100MHz) in series and a small capacitor (such as 10pF) in parallel at the clock output, attenuating harmonics by more than 15dB.

For the path, the clock line should run on the inner layer, referencing a complete ground plane, and avoiding layer changes. If it must run on the surface layer, grounding is used. For the clock chip, a metal shield is used to cover it, and it is grounded through multiple vias. Regarding antenna effects, the clock line length is minimized, and impedance matching at the load end is ensured. Testing shows that this scheme can ensure that the fundamental and harmonic radiation of the PAC's clock in the 30MHz-1GHz frequency band meets the EN55032 Class B limits, with a peak value reduction of 12dB.