
The metrological accuracy of a PMS is closely related to its EMC performance. Harsh electromagnetic environments introduce noise and errors, and excellent EMC design is a prerequisite for ensuring high-precision metrology. EMC interference affects accuracy through various means: conducted noise superimposed on the sampling signal causes reading fluctuations; radiated fields induce error voltages in the sampling loop; ground noise causes reference voltage drift; and rapid transients cause internal logic disorder in the metrology chip. Specifically, under interference, the metrological error may deteriorate from 0.5% to more than 5%, or even lead to pulse counting errors.
Therefore, a high-accuracy PMS must possess robust EMC performance. This requires incorporating EMC principles into the initial design of the metrology circuit: using low-noise, high-PSRR LDOs to power the metrology chip; employing differential transmission for the sampling signal and using a high-CMRR amplifier; strictly partitioning the PCB layout, with the analog section protected by a ground guard ring; and using filtering and ESD protection (such as ESD5V0D3B) for the interface. Passing EMC tests (such as the IEC 61000-4 series) is a necessary means to verify the stability of metrological accuracy under interference environments. A high EMC rating PMS can maintain a metering error of less than 0.5% over a long period of time in complex industrial power grids.