How to optimize EMI in an electrical force measurement switch PMS metering module?

EMI optimization of the PMS metering module (including high-precision ADC, metering chip, and reference source) is directly related to the passing of metering certification (such as MID). Its interference mainly comes from power supply noise, digital interface crosstalk, and external field coupling. Optimization needs to focus on power purification, clock management, and interface filtering. First, design an independent LDO power supply for the metering analog power supply, and use PBZ1608E600Z0T ferrite beads, 10μF tantalum capacitors, and 0.1μF ceramic capacitors before and after it to form a π-type filter, which can suppress ripple to below 5mVpp. The clock crystal oscillator of the metering chip should be a low-jitter temperature-compensated crystal oscillator (TCXO), surrounded by a ground plane in the peripheral circuit, and the edge is mitigated by a 22Ω resistor in series.

Each data line of the digital communication interface (such as SPI) should be connected in series with a PBZ1005B-501Z0T ferrite bead (500Ω@100MHz), and an ESD5V0D3B protection diode should be connected in parallel near the metering chip. In terms of PCB layout, the metering circuit area should form an "analog island," interacting with the digital power domain through a single-point connection using a CMZ2012A-900T common-mode inductor (90μH). With this optimization, the conducted interference generated by the metering module itself is 6dB below the EN 55032 Class A limit in the 150kHz-30MHz frequency band, and the metering error variation is less than 0.2% in the IEC 61000-4-6 conducted immunity test.