How to design power frequency magnetic field immunity for power force measurement switches (PMS)?

The PMS needs to cope with power frequency magnetic field (50/60Hz) interference as specified in the IEC 61000-4-8 standard. This magnetic field may originate from nearby transformers or high-current buses, inducing interference voltages in the internal loops of the equipment. Design focus is on reducing the area of sensitive loops and shielding against magnetic fields. Reducing loop area: All sampling loops (especially current sampling) should be routed in close pairs, with current outflow and return paths as close as possible. On the PCB, a guard ring should be installed for critical analog circuits. Magnetic field shielding: For particularly sensitive circuits (such as metrological references), local shielding can be made using high-permeability materials (such as permalloy).

When laying out the equipment internally, keep the PMS away from known strong magnetic field sources (such as internal transformers). If the PMS itself generates a strong magnetic field (such as a high-power relay), it should be enclosed in a ferromagnetic shielded enclosure. Furthermore, in circuit design, differential inputs and instrumentation amplifiers should be used, utilizing their high common-mode rejection ratio (CMRR) to cancel the common-mode voltage induced by the magnetic field. Through comprehensive design, the PMS can operate normally in a power frequency magnetic field environment of 100A/m with a measurement error variation of less than 0.5%.