How to suppress voltage sampling interference in an electrical force measurement switch (PMS)?

Voltage sampling in a PMS typically uses a high-impedance voltage divider network to proportionally reduce the mains voltage (e.g., 220VAC) to a low voltage (e.g., 0-3.3V). This process easily introduces common-mode interference and differential-mode noise. Suppression requires attention to the design of the voltage divider network, filtering, and shielding. High-precision, low-temperature-coefficient thin-film resistors (e.g., ±0.1%, 25ppm/°C) should be used as voltage divider resistors, and a symmetrical layout should be employed to reduce parasitic capacitance imbalance. A first-order RC low-pass filter should be inserted between the voltage divider point and the ADC input, with a resistor of 100Ω-1kΩ and a capacitor of 1nF-10nF. The cutoff frequency should be set at approximately 1kHz to filter out high-frequency noise.

For common-mode interference, matching Y capacitors (e.g., 2.2pF/2kV) can be connected to ground at the high-voltage and low-voltage ends of the voltage divider network, respectively, or an isolation amplifier can be used. On the PCB layout, voltage divider resistors and filter components should be placed close to the ADC input pins, with traces kept as short as possible and surrounded by a grounded guard trace. If the sampling line is externally connected, shielded twisted-pair cable should be used. These measures can attenuate high-frequency noise (>10kHz) superimposed on the sampling signal by 40dB, and reduce the power frequency waveform distortion to less than 0.5%, thus meeting the requirements for accurate measurement.