How to design power frequency magnetic field immunity for EPS?

The EPS's immunity design against power frequency magnetic fields (such as IEC61000-4-8) is primarily aimed at operating in environments with strong power frequency magnetic fields (such as near high-current buses and transformers). Design measures include:

1. Reducing sensitive loop area: This is the most effective method. Optimize the PCB layout to minimize the loop area of critical low-frequency analog circuits (such as current sampling, voltage reference, and op-amp feedback).

2. Magnetic shielding: For particularly sensitive components or the entire control board, use high-permeability materials (such as permalloy) to create shields, guiding the magnetic field around sensitive areas.

3. Using differential signals and twisted-pair cables: For susceptible signal transmissions (such as PT/CT sampling lines), use differential input amplifiers and twisted-pair cables, utilizing their high common-mode rejection ratio (CMRR) to cancel induced common-mode interference voltages.

4. Signal filtering: Use low-pass filters to filter out power frequency and harmonic components before the signal enters the ADC or control chip.

5. Keeping away from interference sources: When arranging the control board in the cabinet, keep it as far away as possible from high-current conductors and transformers.