
Optimizing the onboard filtering circuit of an HMI requires consideration of three aspects: component selection, circuit topology, and PCB implementation. First, based on noise spectrum analysis, select the filter component with the best impedance characteristics at frequencies exceeding the standard. For example, for noise in the tens of MHz range, use the PBZ1608 series ferrite beads; for noise above 100 MHz, use the PBZ1005 series. Use a composite filtering topology, such as LC-LC multi-stage filtering on the power path, but pay attention to inter-stage impedance matching to prevent resonance peaks. For high-frequency digital signal lines, π-type or T-type filters can be used, with series ferrite beads and parallel capacitors to ground. Optimizing the PCB layout is crucial: filtering components must be placed as close as possible to the pins of noise sources or sensitive devices. For example, decoupling capacitors should be placed close to the IC power pins, and ferrite beads should be connected in series at the power input. Grounding vias for filter capacitors should be numerous and short, directly connected to a complete ground plane to minimize ground inductance. The input and output traces of the power filtering circuit should be clearly separated to avoid coupling. Use power/ground plane layers to provide a low-impedance return path for high-frequency noise. Estimate the filtering effect using simulation tools and iteratively optimize based on actual measurements. Eintech's PBZ and CMZ series devices offer a wealth of impedance-frequency curve data, making it easy for engineers to select the optimal model for specific frequency bands and achieve precise and efficient optimization of onboard filter circuits.