Will AI inference latency increase during conducted immunity testing of industrial AI edge gateways?

In the IEC61000-4-6 10V conducted immunity test of the industrial AI edge gateway, interference signals coupled to the power supply or I/O ports may cause fluctuations in AI inference latency. Actual measurements showed that without protection, 10MHz interference increased DDR refresh latency by 200μs. After protection, latency fluctuation was <10μs. Measures included:

1) Adding a common-mode choke (CMZ3225A-501T) to the 24V power input;

2) Connecting a PBZ1608E600Z0T ferrite bead and capacitor in series with the DDR_VTT power supply;

3) Adding a common-mode filter (CMZ2012A-900T) to the Ethernet PHY;

4) Connecting a 15pF capacitor in parallel to filter critical interrupt pins.

As a result, the average AI inference latency is 45ms ± 1.5ms, meeting industrial real-time requirements.