How to control the minimum loop of an EPS power board?

Controlling the high-frequency current loop area on the EPS power board is key to reducing radiated and conducted noise. Loops with high di/dt and dv/dt act like efficient antennas. Control methods include:

1. Extremely compact layout: Arrange switching transistors, freewheeling diodes, DC-Link capacitors, and drive circuits as close together as possible, especially components forming high-frequency switching current paths. For example, connect the DC-Link capacitor directly across the DC input pin of the MOSFET or IGBT.

2. Use multilayer busbars: For high-power EPS, use multilayer composite busbars instead of traditional cables or single-layer copper busbars. Alternately stack the positive and negative DC layers and the ground layer, utilizing interlayer mutual inductance to cancel each other out, minimizing parasitic inductance and loop area in the power circuit.

3. Mirrored return plane: Place a complete ground plane directly below or adjacent to the power traces to provide a close-proximity mirrored return path for high-frequency current, thereby canceling magnetic field radiation.

4. Optimize device pins: Select device packages with low parasitic inductance (such as TOLL, D2PAK) and optimize pin routing.